Communication interface chip UART485/232

The FIN1217 and FIN1215 convert 21-bit wide parallel LVTTL (low voltage TTL) data into three serial LVDS (low voltage differential signaling) data streams. The phase-locked transmit clock is transmitted in parallel with the data stream over an independent LVDS link. On every transmit clock cycle, 21 bits of input LVTTL data are sampled and transmitted. The FIN1218 and FIN1216 receive these three serial LVDS data streams and convert back to 21-bit LVTTL data. Table 1 is a summary of the serial-parallel/parallel-serial converters offered. For FIN1217, 21-bit LVTTL data is transmitted at 595 Mbps per LVDS channel at a transmit clock frequency of 85 MHz. These chipsets address the EMI and cable size issues associated with wide, high-speed TTL interfaces.