Logic device/transceiver/encoder

The high-performance silicon-gate CMOS MC74C4020A has the same pin-out as the standard CMOS MC14020B. The device inputs are compatible with standard CMOS outputs; pull-up resistors are included for compatibility with LSTTL outputs. The device consists of 14 master-slave flip-flops with 12 stages that are brought out to the pin. The output of each flip-flop feeds the next flip-flop, with half the frequency at each output of the previous one. Reset is asynchronous and active high. Due to internal ripple delays, the state changes of the Q outputs do not occur simultaneously. Therefore, the decoded output signal is prone to decode spikes and may have to be gated with the HC4020A's clock for some designs.