Logic device/transceiver/encoder

The MC14094B combines 8 stages of shift registers, each with a data latch, and each latch has a tri-state output. Data is shifted on positive clock transitions from the seventh stage to the two serial outputs. QS output data is used in high-speed cascaded systems. The QS output data is shifted on the next negative-going clock transition and is used in low-speed cascaded systems. Data from each stage of the shift register is latched on the negative-going transition of the strobe input. Data propagates through the latch when the strobe is high. The outputs of the eight data latches are controlled by tri-state buffers that are placed in a high-impedance state by a logic low on output enable.

8-Bit Parallel Load Shift Register 16-TSSOP -40 to 125