Logic device/transceiver/encoder

4-bit latch/4 to 16-line decoder

8-Channel, 1.65-V to 3.6-V Buffer with Bus Hold and 3-State Outputs 20-TVSOP -40 to 85

SN74ALS240A Octal Buffer/Driver with 3-State Outputs

SN74HC574 Octal Edge D-Type Flip-Flop with 3-State Outputs

Automotive Dual Class D Positive Edge Triggered Flip-Flop with Clear and Preset 14-TSSOP -40 to 125

TXB0104-Q1 Automotive 4-Bit Bidirectional Voltage Level Translator with Auto Orientation Sensing and +/-15kV ESD Protection

Single 2-Input, 2V to 5.5V AND Gate 5-SOT-23 -55 to 125

SN74F11 Triple 3-Input Positive-AND Gate

The MC74VHC14 is an advanced high-speed CMOS Schmitt inverter fabricated on a silicon-gate CMOS process. It achieves high-speed operation similar to an equivalent bipolar Schottky TTL while maintaining the low power consumption of CMOS. The pin configuration and functions are the same as MC74VHC04, but with hysteresis on the input, with its Schmitt trigger function, the VHC14 can be used as a line receiver to receive slow input signals. This internal circuit consists of three stages, including a buffer output that provides high noise immunity and stable output. The input withstand voltage is up to 7V, and it supports the interface from 5V system to 3V system.

The MC10E/100E016 is a high-speed synchronous, presettable, cascadable 8-bit binary counter. Same structure and operation as the MC10H016 in the MECL 10H family, scalable to 8 bits, as shown in the logic symbol. The counter has internal feedback from the TCbar gated by the TCLD (Terminal Count Load) pin. When TCLD is low (or left open, in which case it is pulled low by an internal pulldown), TCbar feedback is disabled, counting continues, and TCbar goes low, indicating a unity state. When TCLD is high, the TC feedback causes the counter to automatically reload when TCbar = low, thus operating as a programmable counter. The Qn output does not need to be terminated for the counting function to function properly. To minimize noise and power dissipation, unused Q outputs should be left unterminated. The 100 Series includes temperature compensation.

The MC10E/100E016 is a high-speed synchronous, presettable, cascadable 8-bit binary counter. Same structure and operation as the MC10H016 in the MECL 10H family, scalable to 8 bits, as shown in the logic symbol. The counter has internal feedback from the TCbar gated by the TCLD (Terminal Count Load) pin. When TCLD is low (or left open, in which case it is pulled low by an internal pulldown), TCbar feedback is disabled, counting continues, and TCbar goes low, indicating a unity state. When TCLD is high, the TC feedback causes the counter to automatically reload when TCbar = low, thus operating as a programmable counter. The Qn output does not need to be terminated for the counting function to function properly. To minimize noise and power dissipation, unused Q outputs should be left unterminated. The 100 Series includes temperature compensation.

Single Supply 2 Input Positive AND Gate with Logic Level Converter 5-SC70