Logic device/transceiver/encoder

4-Channel, 2-Input, 2V to 6V NAND Gate with Open-Drain Output 14-SOIC -40 to 85

2-Channel, 2-Input, 1.65V to 5.5V NAND Gate 8-SM8 -40 to 125

4-Channel, 2-Input, 4.5V to 5.5V NAND Gate with TTL Compatible CMOS Inputs 14-TSSOP -40 to 85

The LVT573 and LVTH573 contain eight latches with 3-state outputs, suitable for system applications with bus structures. When the latch enable (LE) is high, the latch is transparent to the data. When LE is low, the data that meets the input timing requirements are latched. When output enable (OE#) is low, data is presented on the bus. When OE# is high, the bus output is in a high impedance state. The LVTH573 data inputs include a bus hold function that holds unused inputs without the need for external pull-up resistors. These octal latches are designed for low voltage (3.3V) V

18-Bit Universal Bus Transceiver with 3-State Outputs 56-SSOP -40 to 85

Octal Bus Transceiver with 3-State Outputs 20-SSOP 0 to 70

Single-Chip Instrumentation Bus Transceiver 16-SOIC

SN74AHCT373 Octal Transparent D-Type Latch with 3-State Outputs

CMOS BCD Ratio Multiplier 16-SO -55 to 125