Memory chip

The N24S64B is a 64 Kbit serial CMOS EEPROM internally organized as 8,192 words of 8 bits each. It has a 32-byte page write cache and supports Standard (100 kHz), Fast (400 kHz), and Fast-Plus (1 MHz) I2C protocols. The devices also feature a 128-bit factory-set read-only Unique ID, a 32-byte security data page that can be permanently locked to prevent future changes, and software write protection of the entire array. The device configuration registers allow the user to specify the last 3 bits of the device address, allowing up to eight N24S64B devices to be addressed on the same bus.