onsemi (Ansemi)

TSSOP-48-6.1mm

taping

1000

The FIN1217 and FIN1215 convert 21-bit wide parallel LVTTL (Low Voltage TTL) data into three serial LVDS (Low Voltage Differential Signaling) data streams. The phase-locked transmit clock is transmitted in parallel with the data stream over the LVDS link. In every transmit clock cycle, 21 bits of input LVTTL data are sampled and transmitted. The FIN1218 and FIN1216 receive these three serial LVDS data streams and convert back to 21-bit LVTTL data. Table 1 is a summary table of the serial-parallel/parallel-serial converters offered. For FIN1217, when the transmission clock frequency is 85MHz, each LVDS channel transmits 21-bit LVTTL data at a rate of 595Mbps. These chipsets address the EMI and cable size issues associated with wide, high-speed TTL interfaces.