RTC clock synchronization buffer driver delay chip

Low Noise Clock Jitter Cleaner with Dual Loop PLL and Integrated 2.9GHz VCO 64-WQFN -40 to 85

The MC10/100EP139 is a low-skew divide-by-2/4, divide-by-4/5/6 clock generation chip for frequency division, specifically for low-skew clock generation applications. The internal dividers are synchronized with each other so that the common output edges are all precisely aligned. The device can be driven by differential or single-ended ECL, or by an LVPECL input signal if a positive supply is used. Alternatively, a sinusoidal source can be ac-coupled into the device by using the VBB output. If a single-ended signal is to be used, the VBB pin should be connected to the CLKbar input and bypassed to ground with a 0.01 uF capacitor. The common enable (ENbar) is synchronous, so the internal divider is only enabled/disabled when the internal clock is already in a low state. This avoids short clock pulses on the internal clock when the device is enabled/disabled, which can happen with asynchronous control. The internal enable flip-flops are clocked on the falling edge of the input clock, therefore, all relevant specification limits are referenced to the negative edge of the clock input. At startup, the internal flip-flops will reach random states; therefore, for systems using multiple EP139s, the master reset (MR) input must be asserted to ensure synchronization. For systems using only one EP139, the MR pin, which is not required to operate as an internal divider design, will ensure synchronization between a device's 2/4 output divide and 4/5/6 output divide. All VCC and VEE pins must be powered externally for proper operation. The 100 series includes temperature compensation.