RTC clock synchronization buffer driver delay chip

High performance, low phase noise, low skew clock synchronizer (synchronizes reference clock to VCXO) 64-BGA -40 to 85

The MC100LVEL40 is a three-state phase-frequency detector for phase-locked loop applications that require minimal phase and frequency difference when locking. The advanced design significantly reduces the detector's dead zone. For proper operation, the input edge rate on the R and V inputs should be less than 5 ns. The device is designed to operate from a 3.3 V supply. When the frequency and/or phase of the reference (R) and feedback (FB) inputs are different, the differential UP (U) and DOWN (D) outputs provide pulse streams that, if subtracted and integrated, provide a control The error voltage of the VCO. Only the VBB pin, the internally generated supply voltage, is provided for this device. In the case of single-ended inputs, tie the unused differential input to VBB as the switch reference voltage. VBB can also re-bias the AC-coupled input. When used, decouple VBB and VCC with 0.01 5F capacitors and limit current source or sink to 0.5 mA. VBB should be left open when not in use. See AND8040/D "Phase-Locked Loop Operation" for applications information. The 100 series includes temperature compensation.