RTC clock synchronization buffer driver delay chip

The MC100EP40 is a 3-state phase-frequency detector for phase-locked loop applications that require minimal phase and frequency difference when locking. The advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rate on the R and V inputs should be less than 5 ns. The device is suitable for use with a 3.3 V / 5 V supply. When the frequency and/or phase of the reference (R) and feedback (FB) inputs are different, the differential UP (U) and DOWN (D) outputs provide pulse streams that, if subtracted and integrated, provide the control VCO the error voltage. When the phase difference between the reference (R) and feedback (FB) inputs is 80 pS or less, the phase lock detect pin will indicate a lock with a high state. As shown in Figure 2, the VTX (VTR, VTRbar, VTFB, and VTFBbar) pins provide an internal termination network for a 50-wire impedance environment. The VTX pin requires an external current sink of VCC-2 V. If the two differential VTRs and VTR (or VTFB and VTFBbar) are shorted together, a 100 Ω termination resistor compatible with the termination of the LVDS signal receiver is provided. See AND8020 for more information on logic device termination. The VBB pin is used as an internally generated power supply for this device only. For the single-ended input case, connect the unused differential input to VBB as the switch reference voltage. VBB can also re-bias AC-coupled inputs. When used, decouple VBB and VCC with 0.01 μF capacitors and limit current source or sink to 0.5 mA. VBB should be left open when not in use. See AND8040 for more information on phase locked loop operation. Special consideration should be given to differential inputs to prevent instability under no-signal conditions.